PCI Express Protocol Analyzer

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The PCIe Volksanalyzer is the perfect debugging and analyzing tool for FPGA based PCI Express solutions. The Analyzer software supports Altera PCIe hard IP core or the Gleichmann Electronics Research PCIe IP core or any simulator, which creates a .vcd output file. Support for more PCIe IP will be added step by step. The PCIe Volksanalyzer IP core can be placed inside the same FPGA as the PCIe core, no external hardware is needed. The PCIe Volksanalyzer is controlled via the Altera JTAG interface, so again no extra hardware is needed.

Introduction:

Gleichmann Electronics Research has experience with PCI Express since 2004. Very early we developed together with the University of Hagenberg a PCI Express IP. Later when we developed the Industrial Reference Platform Hpe_IRP we got a lot of experience with really high speed data transfers between FPGA and an Intel ATOM and other processors with PCI Express interface. After supporting Intel with their Remote Platform http://edc.intel.com/Platforms/Remote-Labs/ and the creation of the tutorials for this lab we developed in parallel to the PCI Express Performance Meter the PCIe Analyzer. Therewith we want to give engineers a simple tool for analyzing the PCI Express data stream. Following the philosophy of the Volksanalyzer tools we offer a very cost effective tool.
The Analyzer consists of four independent modules:
  • The Visualization – Powerful graphical views, independent from where the data stream comes
  • The Simulation – A simulation with a .vcd output (e.g. Mentor ModelSim) can be read into the analyzer
  • The IP – Different possibilities to connect to the data stream. We support hard IP as well as soft IP
  • The Hardware – Tap and analyze any PCIe connection on a PCB

    • Heart of the tool is the Visualization software.

    It's an independent module which runs under Windows XP/7.

  • One tool for analyzing HW records and simulation traces
  • Compact view for basic debugging and bring up new PCIe devices
  • Time line view for optimizing through put and latency
  • Well-conceived user interface for effective navigating through long records


    • More interesting screenshots are here!    		 click to enlarge
    Picture 1: Screenshot from the PCIe Analyzer window (click here to enlarge picture)

    For the first analysis most developer sets up a simulation.

    The PCIe Analyzer is able to import results in .vcd format.

    This feature makes it possibel to analyze the PCIe data stream with the easily

    understandable graphical interface.

    		 click to enlarge
    Picture 2: Screenshot from a ModelSim simulation.(click here to enlarge picture)

    The PCIe Analyzer- IP collects the data directly

    out of the PCIe soft or hard core. To minimize the amount of required

    internal memory the IP contains complex trigger and filter functions.

    It is possible to use the IP stand alone or inside the AMBA IP Manager,

    which guarantees an easy handling and programming. If the IP is used

    inside the Hpe_IRP2 system it will be possible to use external memory to

    monitor much longer data streams.

    		 click to enlarge
    Picture 3: AMBA IP Manager, containing a design and the PCIe Analyzer IP (click here to enlarge picture)

    The PCIe Volksanalyzer is not limited to FPGA systems.

    It can analyze any PCIe connection by using additional hardware.

    This hardware consists of two components: an "Analyzer Box" and

    an adapter/probe. The "Analyzer Box" can be seen as the physical implementation

    of the *Volksanalyzer IP*. It contains the recording, filtering and triggering logic

    as well as the trace memory. Different adapters handle the different mechanical form

    factors can be standard PCIe ones like slot cards or miniPCIe cards, as well as

    module standards like ComExpress or Qseven.

    It will be also possible to add some driver IC plus a connector to any customer board.

    This allows connecting the "Analyzer Box" and to analyze the data stream and to

    measure performance on the PCIe data lines.

    The delivery of the Analyzer box is planned for the fourth quarter 2012.

    The Analyzer software is identical and will be updated automatically.

    		 Analyzer Box
    Picture 4: First draft ot the "Analyzer Box"