JTAG / Boundary Scan Analyzer

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Cost efficient JTAG-Tool
- For interactive board level debugging and production tests
IO-Filtering
- Observe IOs of interest only
Pin-File parsing
- Use your HDL top-level pin names to find signals quickly
Free with every Hpe® system
- Every ARM MPS, Hpe®_midiv2, Hpe®_IRP and Hpe®_IRP2 will be delivered with powerful and free software tools, including Hpe®_JTAG
Scripting interface
- For production test and all repetitive tasks
New Board Diff function automatically
- find shorted I/O pins (on one device and between many devices)
- find stuck-at-zero I/O pins, stuck-at-one I/O pins and clock pins
- is an intuitive and highly user friendly GUI
- offers protection from board damage by allowing the user to specify safe state for testing
pins that are connected to sensitive electronic modules on a board
- has a simulation mode for users evaluation before they get physical hardware
- then perform comparative tests against a know good board.

Complete description here

Have you ever attempted to measure signals between two ball grid arrays and then noticed that you forgot to insert test pads?
Has the price of JTAG tools kept y ou from using Boundary Scan Tests? With Hpe_JTAG Gleichmann Electronics Research
introduces a cost efficient JTAG tool allowing you to debug and test your PCBs and ICs. Hpe_JTAG gives the design engineer
full control over the logical states of any I/O-pin or register that is accessible via Boundary Scan at a fraction of the cost of high-end
JTAG tools. Opposed to most low-cost JTAG tools, Hpe_JTAG is fully scriptable, hence tests can be automated for production.

The X-Ray pictures below show two of the most common problems designers might run into when using BGAs: shorts and open solder joints.

JTAG JTAG


Not every designer has access to an x-ray machine and if these signals are not routed to the top or bottom layer of the PCB, JTAG might be the only
way to find these sorts of problems. Hpe_JTAG enables designers to debug their PCBs interactively (without the need to program a design into the PLDs),
observe and debug their PLD designs, write scripts for all repetitive tasks and even setup production tests at a fraction of the cost of high-end JTAG tools.

Hpe_JTAG supports the following JTAG instructions:

  • SAMPLE: The SAMPLE instruction is used to get a snapshot of the current pin states of a device in the JTAG chain. It does not influence the device operation.
  • EXTEST: The EXTEST instruction is used to check a connection between devices in one JTAG chain. The values of output pins can be set and the values of input pins can be read.
  • INTEST: The INTEST instruction is used to check the internal functionality of a device in the JTAG chain. The values of input pins can be set and the values of output pins can be read. Note that the availability of the INTEST instruction depends on the devices' capabilities.

    • Hpe_JTAG provides a graphic user interface, but also powerful Python-scripting capabilities. The screenshot below shows an example for a
    scan chain containing two JTAG compatible devices that are represented by the two tabs. Instead of graphically representing huge ball grid arrays
    with more than thousand IOs each, a filter function allows the user to display only IOs that are currently of interest.


    JTAG

    IO-Filtering:

    Observe IOs of interest only

    Pin-File parsing:

    Use your HDL top-level pin names to find signals quickly



    Elektronik Praxis

    Markt und Technik    		 Elektronik Praxis      Ece
      EP24-2008.pdf
    (German only)    		ECE-2009.pdf